This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source.The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35μm 2P4M technology. The power consumption was approximately 7.9mW at the sample rate of 200MHz, and the supply voltage was 3.3V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3dB under a 1MHz sine waveform.This work presented a good performance compared with other researches in DNL, INL and power consumption.