Testing delay faults in FPGAs differs significantly from testing delay faults in circuits whose combinational sections are represented as gate networks. Based on delay fault testability conditions, formulated in a form suitable for analysis of LUT-based FPGAs, a new method for the evaluation of delay fault testability of LUT functions has been developed. It relies on an indicator called delay fault activation profile. The proposed method supports an analysis and comparison of different procedures for the enhancement of detectability of FPGA delay faults that rely on transformations of user-defined functions of LUTs in the section under test. The effectiveness of the method is demonstrated by applying it to prove the efficiency and to optimize a specific procedure for the transformation of user-defined LUT functions.