Computers are broadly classified into two classes: general-purpose and special-purpose. General-purpose computers provide tolerable performance on a wide range of programs. In contrast, specialized computers, tailored to a narrow class of programs, usually yield significantly higher throughput. However, specialized computer architectures are limited in availability, inflexible, require special programming environments, and are, in general, expensive. Both classes are limited in that they utilize a ‘fixed’ hardware architecture, i.e. their designs, conceived at creation, are unchanged during their lifetime. PRISM-I introduced a new concept, wherein a custom architecture is dynamically created to execute a specific high-level program in a faster and more efficient manner. While one component of this architecture is a traditional general-purpose processor, the other is automatically synthesized from a collection of FPGAs by a configuration compiler. Speed-up is achieved by executing key sections of the high-level program on the synthesized hardware, while the remainder of the program executes on the core processor. While PRISM-I developed a proof-of-concept platform, it is significantly limited to simple programs. This paper introduces a significant conceptual advancement, PRISM-II, which synthesizes asynchronous, adaptive architectures for complex programs, including those that contain iterative ‘loop’ structures with dynamic loop counts. PRISM-II introduces a novel execution model, wherein an operator-network and controller are synthesized for key sections of a high-level program. The operator-network, custom-synthesized from FPGAs, executes the key sections in a data-flow manner, i.e. any instruction is executed as soon as its input operands are available. The controller controls the computations in the operator-network, accurately determines when the execution is complete by utilizing key principles developed in PRISM-II, and generates an end-of-computation signal to asynchronously inform the core-processor to fetch the results from the FPGA platform. While the realization of a general-purpose data-flow architecture has continued to be difficult in the architecture community, the PRISM-II approach promises asynchronous, data-flow execution of programs on custom synthesized FPGA hardware.