This paper describes improvements to the parallel prefix adder designs and optimization algorithms of Chan, Oklobdzija, Schlag, Thomborson and Wei. Our [ldquo ]direct feeding[rdquo ] (DF) adder design avoids large signal fanouts along critical adder paths. Our [ldquo ]random pruning[rdquo ] heuristic limits the time and space required to find near-optimal DF adders, so that the search process runs in a few minutes on a Sun-4 workstation. Our improved carry lookahead adders are well suited for static CMOS implementation; our improvements may be applied to other parallel prefix CMOS circuits. Simulations with Mentor Graphics' Lsim indicate that our best DF adders are 12% to 20% faster than the carry lookahead adders presented by Chan et al.