In less than 10 years, we will be approaching the limits of CMOS technology with transistor gate length between 20 and 30 nm. The definition of the transistor gate region will remain one of the most critical steps of the device fabrication process since the final gate dimension cannot be derived from the dimension targeted by more than few nanometers. Etching of silicon gates is achieved in high density plasmas, allowing vertical profiles to be obtained, transferring the critical dimensions (CD) obtained after lithography. The ultimate resolution of this approach is limited by the lithographic performance of the exposure tool and by the etching process. In the present paper, we present a new type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called 'notched gate'). We discuss the design of the notched gate process with respect to a standard gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of CD control across a 200-mm diameter wafer are shown and the potential implementation of the process in pilot lines is discussed.