In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: http://www.pi.infn.it/SuperB]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, doi:10.1016/j.nima.2010.05.039].In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm 2 with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack ⋅ s −1 ⋅ cm −2 with a temporal resolution below 1 μs. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.