Selective chemical vapor deposition (CVD) of TiSi 2 has been obtained from TiCl 4 /DCS/H 2 chemistry using an industrial integrated cluster reactor. First, some fundamental aspects were studied in order to better understand the process. Prior to deposition, an incubation time exists which increases with decreasing deposition temperature. For temperatures between 650 and 780°C, the growth rate is limited by the TiCl 4 flow. This CVD technique was then used on device wafers and we obtained low sheet resistances of down to 0.2 μm in poly linewidth and 0.12 μm in active area width. Leakage currents on diode structures are shown to be essentially dependent on residual implantation defects, and thus, on implantation conditions. To conclude, CVD TiSi 2 has been validated on a microprocessor circuit fabricated in a 0.35 μm CMOS process and the yield obtained is comparable to that obtained using the standard salicide technique with fewer technological steps.