Przegląd Elektrotechniczny > 2018 > R. 94, nr 9 > 26--28
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journal ISSN : | 0033-2097 |
journal e-ISSN : | 2449-9544 |
DOI | 10.15199/48.2018.09.06 |
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[1] Iakymchuk T., Rosado-Muñoz A., Mompéan M.B., Víllora J.V.F., Osimiry E.O., Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices, IEEE Transactions on Computers, 65 (2016), no. 11, 3470-3479
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[2] Yang H., Ziavras S.G., Hu J., FPGA-based Vector Processing for Matrix Operations, Information Technology, 2007. ITNG '07. Fourth International Conference on, Las Vegas, (2007), 989-994
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[3] Zhang Y., Shalabi Y.H., Jain R., Nagar K.K., Bakos J.D., FPGA vs. GPU for sparse matrix vector multiply, 2009 International Conference on Field-Programmable Technology, Sydney, (2009), 255-262