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Modern Chip Multiprocessors (CMPs) contain multiple cores in a single chip and these cores share last-level cache (LLC). When applications with different memory access behaviors compete for the shared LLC, conventional Least Recently Used (LRU) management policy leads to performance degradation. Applications with different memory access behaviors compete for the shared LLC in different ways, and many...
With growth of on-chip communication delays and working sets of commercial and scientific workloads, L2 caches of Chip Multiprocessors (CMPs) are subject to heave pressure. Basically, there are two kinds of designs for L2 cache. First, using shared L2 cache to maximize the aggregate cache capacity and minimize off-chip memory requests. Second, using private L2 cache to minimize delays on global wires...
To provide more vivid perception, more and more advanced features, like the 4ktimes2k resolution and the multiview functionality, are emerging for TV. For a multiview video coding (MVC) encoder, motion and disparity estimation (ME/DE) take at least half the hardware requirement. To solve these challenges, a cache-based integer ME/DE algorithm is proposed. With a cache memory as the search window buffer,...
The proposed MVC encoder chip is characterized as follows: 1) View-parallel MB-interleaved (VPMBI) scheduling with 8-stage MB pipelining is introduced to overcome the first 2 challenges. With this technique, the processing capability is 212 Mpixels/s, at least 3.4times better than the previous works. In addition, view scalability is achieved and supports real-time processing from single-view 4096times2160p...
High Definition (HD) video compression enables vivid reproduction of scenes. However, Motion Estimation (ME) requires large memory capacity and huge memory bandwidth, which are undesirable in many platforms including ASIC and SoC. In this paper, an algorithm and architecture design of cache system and fast ME in HD H.264/AVC are proposed. With the proposed cache system and hardware-oriented fast ME...
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