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This paper presents a low-power, passive, EPCtrade C1G2-compatible UHF RFID tag design implemented in a 90 nm CMOS technology. In order to reduce its cost, diode-connected NMOSFETs in a standard CMOS technology is used instead of Schottky diodes. A sub-1 V, low temperature-coefficient voltage reference, using self-biased mutual compensation without large resistors, is proposed to save the chip area...
An ultra-low-power clock generator for passive UHF RFID tag is implemented in 0.18-mum CMOS process. By using the technique of dual-path clock generation with multiple clock rates and multiple supply voltages, clock accuracy is much improved and power consumption is reduced. Under the injection-locked condition, the measured cycle-to-cycle jitter of the clock generator is 23.7 ps and the peak-to-peak...
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