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The Physically-Asynchronous Logically-Synchronous (PALS) system is a recently proposed architectural pattern for cyber-physical systems. It guarantees a logically synchronous design abstraction for real-time distributed computations. In this work, we develop a new middleware, called PALSware, to support an efficient and robust implementation of the PALS system and its extensions. PALSware guarantees...
All of today's known clock gating techniques only disable clocks on valid (”correct”) clock gating conditions, like idle states or observability don't cares (ODC), whose applying will not change the circuit functionality. In this paper, we explore a technique that allows shutting down certain clocks during invalid cycles, which if applied alone will certainly cause erroneous results. However, the...
Most dynamic voltage and frequency scaling (DVS) techniques adjust only CPU parameters, however, recent embedded systems provide multiple adjustable clocks which can be independently tuned. When considering multiple components, energy optimal frequencies depend on task set characteristics such as the number of CPU and memory access cycles. In this work, we propose a realistic energy model considering...
Most of the vector overlay operations are designed in the vector-topological model, which require the individual layers structured with full topology. It takes rather a long time to build the topology to each of the input data sets, and the output of the process is a new topological structured layer whose topology information seldom needed. In order to avoid the time-consuming topology building process...
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