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The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects — stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond...
Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Relaxed Ge p-FinFETs and even Ge with a GeSn5% source / drain stressor cannot outperform strained Si. However, growing the Ge channel strained on a SiGe75% strain relaxed buffer (SRB) provides a 49% mobility boost over strained Si. For Si n-FinFETs, SRB mobility...
We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction...
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