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An 8-bit charge-redistribution DAC with double bit processing in a single capacitor is proposed. The proposed DAC requires only four binary weighted capacitors where each capacitor converts 2-bit digital data into an analogue value in a single conversion step. Therefore, capacitor area can be effectively reduced without affecting the conversion time. The proposed 8-bit DAC is fabricated using CMOS...
A switch-capacitor cyclic DAC with mismatch charge compensation scheme is proposed. With this approach, the DAC error caused by capacitor mismatches can be effectively reduced, which alleviates the matching requirement. The operation of the proposed DAC is verified through circuit level simulations.
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