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To reduce the huge search space when customizing instruction-level accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated instruction-level hardware/software partition method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy. The search space is...
To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction...
Recently to face the challenges of high efficiency and time-to-market pressure, instruction set auto-customization for application-specific instruction-set processors (ASIP) has become an attractive technology. In this process how to select an optimized instruction set in a short time is crucial to the whole synthesis of ASIP. To address this issue, we formulate the instruction set selection problem...
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