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This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-µm CMOS technology, while one of them...
Ultralow-energy biomedical applications have urged the development of a subthreshold VLSI logic family in standard CMOS. This brief proposes an unbalanced pull-up/down network, together with an inverse narrow-width technique, to improve the operating speed of the individual logic cell. Effective logical efforts save both power and die area in the process of device sizing and topology optimization...
This paper reports the design and optimization of a standard cell library in 0.18µm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage...
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