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The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing...
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