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Self-boost-programming for ferroelectric-NAND (Fe-NAND) flash memory was investigated by using a miniature memory cell array, which could reduce bit-line voltages for programming. As the best performance, 0.5V bit-line-voltage programming with 10μs-pulse width was successfully demonstrated. This study indicated that the Fe-NAND flash memory can be operated by much lower power consumption than that...
The world's most downsized ferroelectric-gate field effect transistors (FeFETs) with good electrical properties were successfully fabricated, which were developed as memory cells of ferroelectric-NAND (Fe-NAND), the next generation NAND flash memory. 0.54 μm- and 0.26 μm-gate FeFETs were fabricated and characterized. The stacked gate structure of the FeFETs was Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. Cross-sectional...
A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The proposed SRAM has a unique configuration to apply the body of NMOS and PMOS with VDD and VSS. During the read and the hold, the VTH of Fe-FETs automatically changes to increase the static noise margin, SNM, by 60%. During the sand-by, the VTH of the proposed SRAM cell increases to decrease...
A zero VTH memory cell scheme for the ferroelectric (Fe)-NAND flash memory is proposed. In the zero VTH memory cell scheme, the middle of VTH of erased and programmed cells is 0 V. Based on the measurement, this paper shows for the first time that the reliability of a Fe-NAND cell such as the data retention, read disturb, and program disturb is best optimized in the proposed zero VTH cell. The measured...
A lateral overflow integration capacitor (LOFIC) based CMOS image sensor sharing two pixels and without row-select transistors has been developed using a newly added lateral overflow gate which directly connects the photodiode and the LOFIC. A 0.18-mum, 2-Poly 3-Metal CMOS technology with a buried pinned photodiode process was employed for the fabrication of the CMOS image sensor having 1/3.3-inch...
A nonvolatile ferroelectric complementary metal-oxide-semiconductor (CMOS) circuit with both logic and memory functions is proposed as a new application of ferroelectric field effect transistors. The logic and memory operations of a NOT-logic ferroelectric CMOS device is demonstrated. Nondestructive readings of high and low output voltage levels of the device were performed. Data retention was measured...
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