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A formal verification method of the datapath and controller generation phase of a high-level synthesis (HLS) process is described in this paper. The goal is achieved in two steps. In the first step, the datapath interconnection and the controller finite state machine description generated by a high-level synthesis process are analyzed to obtain the register transfer-operations executed in the datapath...
The paper describes a verification method of data-path and controller generation phase of high-level synthesis (HLS) process. The goal is achieved in two steps. In step 1, the generated RTL description is analyzed to obtain the register transfer (RT) operations executed in the data-path for a given control assertion pattern in each control step and in step 2, an equivalence checking method is proposed...
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