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Self-boost-programming for ferroelectric-NAND (Fe-NAND) flash memory was investigated by using a miniature memory cell array, which could reduce bit-line voltages for programming. As the best performance, 0.5V bit-line-voltage programming with 10μs-pulse width was successfully demonstrated. This study indicated that the Fe-NAND flash memory can be operated by much lower power consumption than that...
The world's most downsized ferroelectric-gate field effect transistors (FeFETs) with good electrical properties were successfully fabricated, which were developed as memory cells of ferroelectric-NAND (Fe-NAND), the next generation NAND flash memory. 0.54 μm- and 0.26 μm-gate FeFETs were fabricated and characterized. The stacked gate structure of the FeFETs was Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. Cross-sectional...
A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power...
A zero VTH memory cell scheme for the ferroelectric (Fe)-NAND flash memory is proposed. In the zero VTH memory cell scheme, the middle of VTH of erased and programmed cells is 0 V. Based on the measurement, this paper shows for the first time that the reliability of a Fe-NAND cell such as the data retention, read disturb, and program disturb is best optimized in the proposed zero VTH cell. The measured...
Statistical distribution of the threshold voltage Vth for both p-and n-channel Pt/SrBi2Ta2O9/Hf-Al-O/Si ferroelectric-gate field-effect transistors (FeFETs) is reported. The standard deviations of Vth are within 7-8% and 3-5% of the memory window for the p-and n-channel FeFETs, respectively. The temperature dependence of FeFETs is also studied from 27 to 85degC. The distribution measurement at the...
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