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On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed, circuit complexity and an increase in interconnect length. In this paper, a novel closed form delay metric has been proposed for the on-chip VLSI RLC interconnect. The model has also been extended for the case when the time of flight of the input signal is comparable. It is started with...
With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the...
The main objective of this paper is to accurately estimate the fault location in a transmission line. Accurate estimation of transmission line fault location will lead to quicker restoration of the supply. At the relay location, the instantaneous values of faulty current, voltage and power signals are available. The available signals are decomposed using 13-level Discrete Wavelet Transform (DWT)....
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