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In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions,...
In this paper, we propose a hardware preemptive multitasking mechanism which uses scan-path register structure and allows identifying the total task's register size for the FPGA-based reconfigurable systems. The main objective of this preemptive mechanism is to suspend hardware task having low priority, replace it by high-priority task and restart them at another time (and/or from another area of...
In this paper, we propose an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream encryption based switched linear congruent pseudo-random generator. This encryption method is particularly attractive since it provides a low-cost security communication solution while increasing the throughput rate and decreasing the area of the FPGA circuit. This technique only requires...
The data security is a significant subject for which various solutions algorithms were proposed. In 2001, advanced encryption system (AES) was accepted like a standard FIPS. AES is a symmetrical algorithm of encoding intended to replace DES which had already shown certain faults of safety in the data protection. Since then, of many achievements on hardware and software were proposed by combining various...
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