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This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased...
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs...
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