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Slack matching, gate sizing and repeater insertion are well known techniques applied to asynchronous circuits to improve their power and performance. Existing asynchronous optimization flows typically perform these optimizations sequentially, which may result in sub-optimal solutions as all these techniques are interdependent and affect one another. In this paper, we present a unified leakage power...
Gate sizing and threshold voltage selection is an important step in the VLSI physical design process to help reduce power consumption and improve circuit performance. Recent asynchronous design flows try to directly leverage synchronous EDA tools to select gates, which have a lot of limitations due to the intrinsic difference between asynchronous and synchronous circuits. This paper presents a new...
Recent asynchronous VLSI circuit placement approach tries to leverage synchronous placement tools as much as possible by manual loop-breaking and creation of virtual clocks. However, this approach produces an exponential number of explicit timing constraints which is beyond the ability of synchronous placement tools to handle. Thus, synchronous placer can only produce suboptimal results. Also, it...
Two kinds of novel converter circuits containing single-electron transistors and MOS transistors are proposed. The proposed Digital to Analog Converter (DAC) circuit and Analog to Digital Converter (ADC) circuit are both improved in the base of the pure SET and SET/MOS hybrid circuits that were designed by other research groups, so they possess the merits of both SET and MOS circuits. Through the...
Due to the single electron transistor has the characteristics coulomb oscillation and adjustable threshold voltage, the single electron transistor is adapted to design the multiple value circuit. In this paper, a ternary multiplier is designed based on multigate single electron transistor, and the design uses the 3-T gate. The designed circuits have been simulated by SPICE. The results of simulation...
This paper present a circuit design of a 8-bit parity code generator using single-electron transistors (SETs). The design is based on the characteristic of multigate single-electron transistor and a single-electron transistor can realize a n-input exclusive-OR (XOR) gate or XNOR gate. The proposed design enable us to construct a 8-bit parity code generator using only four SETs. The simulation is performed...
Based on both the I-V characteristics of single-electron transistors and the MOS digital integrated circuit design concept, a good combination of single-electron transistors with MOS transistors is advanced to create a novel inverter, which, compared with the pure SET circuit, is considerably augmented in its voltage gain and drive capability. Then a close analysis was conducted of the inverter, on...
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