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Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation...
In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus widths, the number of buses, and the memory sizes. As a main contribution, bus and memory architectures are optimized simultaneously by allocating different...
This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules...
Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect congestion, power dissipation in buffered interconnects pose tremendous difficulties on the design process. It is therefore of paramount importance to address...
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