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With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is...
This paper presents a scan architecture - California scan - that achieves high quality and low power testing by modifying test patterns in the test application process. The architecture is feasible because most of the bits in the test patterns generated by ATPG tools are don't-care bits. Scan shift-in patterns have their don't-care bits assigned using the repeat-fill technique, reducing switching...
The advent of multi-core embedded processors has brought along new challenges for embedded system design. This paper presents an efficient, battery aware, code partitioning technique for a text to speech system, which is executed on a multi-core embedded processor. The system achieves significant performance improvements both in terms of execution time as well as battery lifetimes. The mentioned technique...
We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is highly effective in learning to classify complex stimuli in semi-supervised fashion. The circuits presented are designed in sub-threshold CMOS consuming extremely low power. The pulse-based neural network communicates with the...
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