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Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower level metals used for local routing, where bi-directionality gives rise to lithography unfriendly layout patterns. However, one can modify such wires without significantly affecting design behavior. In this paper, we propose to simultaneously...
The studies in fault-tolerance in networks mostly focus on the connectivity of the graph as the metric of fault-tolerance. If the underlying graph is k-connected, it can tolerate up to k - 1 failures. In measuring the fault tolerance in terms of connectivity, no assumption regarding the locations of the faulty nodes are made - the failed nodes may be close to each other or far from each other. In...
This paper presents design of an 8-bit 1.8 V segmented current steering (CS) digital-to-analog converter (DAC) using 0.18 mum double poly five metal CMOS technology. The DAC has been segmented as 6+2 to achieve optimum performance for minimum area. The simulation result shows a maximum DNL of 0.30 LSB and an INL of 0.33 LSB. The midcode glitch is 0.27 pV s. The simulated SNDR and SFDR of the segmented...
Motivated by the optimization of power and improvement of video resolution, this paper proposes a content-based adaptive sampling system for video acquisition. Blind sampling suffers from the lack of resolution and blurring. However, use of a priori knowledge can provide intelligent sampling function that will reduce the blur artifacts. This paper proposes an information theoretic criteria-based sampling...
Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45 nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to high mask cost. Given the impossibility of...
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