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A novel quad-rail CMOS SRAM cell architecture that doubles cell read current, improves cell static noise margin (SNM) by 70%, increases cell immunity to SER, and lowers cell standby power by over an order of magnitude is proposed. These improvements over conventional 6T CMOS SRAM cells, verified with HSPICE simulations on a 0.18µm industrial process are achieved by implementing a scheme of WL transition...
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