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This brief analyzes the circuit-induced challenges to reliability and write current scaling of spin-torque-transfer random access memory (STTRAM). We show that, at sub-90-nm nodes, increased transistor leakage increases the probability of incorrect sensing requiring a higher read current. However, a higher read current can increase the read disturb failure, particularly with a reduced write current...
This work presents modeling of the self-heating effect in Spin Torque Transfer RAMs (STTRAM) and analyzes its impact on the functional reliability. We perform computational fluid dynamics based 3-D thermal simulation in Fluent?? for STTRAM at 90 nm technology and characterize the thermal profile considering write condition. The thermal analysis is connected to device and circuit simulators to estimate...
In this paper we propose a methodology for energy efficient Spin-Torque-Transfer Random Access Memory (STTRAM) array design at scaled technology nodes. We present a model to estimate and analyze the energy dissipation of an STTRAM array. The presented model shows the strong dependence of the array energy on the silicon transistor width, word line voltage and row/column organization. Using the array...
In this paper, we investigate the combination of a novel computing paradigm referred to as Memory Based Computing (MBC) and an emerging non-volatile nanoscale memory technology, namely Spin-Torque Transfer Random Access Memory (STTRAM), to build a reconfigurable nanocomputing framework with high integration density, robustness and energy-delay efficiency. MBC uses a 2-D memory array as underlying...
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