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We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut...
We present a prototype of a switch that encodes information in the position of a magnetic domain wall (DW) in a ferromagnetic wire. The information is written using spin transfer torque and/or spin hall effect and read out using a magnetic tunnel junction (MTJ). We build prototypes and show that a single three-terminal device can perform buffer/inverter operations, which can be used as AND/NAND gates...
This paper presents the design and hardware implementation and testing of 20kVA Gen-1 silicon based solid state transformer (SST), the high input voltage and high voltage isolation requirement are two major concerns for the SST design. So a 6.5kV 25A dual IGBT module has been customized packaged specially for this high voltage low current application, and an optically coupled high voltage sensor and...
In this paper, a module has been presented which can perform a seamless interoperation between Bluetooth and Wi-Fi interfaces. The work is really challenging to achieve as both the interfaces work in the frequency band of 2.4 GHz creating a high possibility of interference. The challenge of implementing such an interoperable application atop OSGi framework has been discussed in this paper as well...
In this paper the effect of pulsed current-voltage (ID-VGS) measurements on the hysteretic behavior of carbon nanotube field-effect transistors (CNTFET) on SiO2, and the subsequent mobility extraction is studied. It is found that hysteresis decreases with longer pulse delays and higher ambient temperature, and can be almost entirely eliminated at -10 s pulse intervals and -180 ??C. Moreover, mobility...
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