The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Pulse Step Modulation based High voltage power supply has played significant role in fusion research. Multi-Secondary transformers are invariably used for generation of tens of kV range outputs with fast (µS order) transient response. In this scheme, large numbers of isolated voltage sources are connected in series to generate the output. Isolated voltage sources can be achieved by large number of...
This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is...
Passive RFID application is often used in back scatter mode where a weak reflected signal is relied upon by reader systems. This limits the application of the technology as the reader and tag distance is constrained. This paper presents a passive design where planar capacitors are used to locally store charges to power a tag based on newer CMOS technology. In this paper BSIM4 transistor model based...
The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.