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In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications. A UWB pulse is generated using the triangular pulse generation technique. The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse. A maximum data rate of 2.5 Gb/s with transmitted reference is achieved when the...
The transmitted reference ultra-wideband (TR-UWB) scheme has generated considerable interest in the field of UWB radio and on-chip wireless interconnect systems. This paper presents a wideband delay element (WBDE) which is a major design concern for TR-UWB transceivers and introduces a novel WBDE architecture that eliminates the need for dual bipolar power supplies. A very wide range of delays of...
Passive RFID application is often used in back scatter mode where a weak reflected signal is relied upon by reader systems. This limits the application of the technology as the reader and tag distance is constrained. This paper presents a passive design where planar capacitors are used to locally store charges to power a tag based on newer CMOS technology. In this paper BSIM4 transistor model based...
This paper demonstrates a 23.5 GHz double stage low noise amplifier using an innovative inter-stage matching technique. The same matching technique is also used at the output of the amplifier for the purpose of output matching. The circuit is designed in IBM .13 mum CMOS process and is simulated using cadence spectre. The simulated responses exhibit a forward gain of 20 dB at 23.5 GHz with a bandwidth...
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectra with 0.13 mum CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit...
This paper demonstrates that inserting a small resistance at the drain of a cascode LNA can be the simplest way of achieving higher bandwidth with only a slight degradation in noise figure. A 36.1 GHz single stage low noise amplifier is designed in 0.13 mum CMOS Process with a simple passive output matching circuit. The circuit is simulated using Cadence Spectre and simulation results show a forward...
Caches which are an essential part of memory systems consume a significant amount of power. A number of techniques have been proposed in the literature to reduce power consumption in cache modules. In this paper a survey of various widely used circuit and architecture level techniques for cache power management system is presented to investigate an effective approach for multi-core system-on-chip...
This paper presents an analysis of the positive and negative impacts of on-chip inductance. It has been illustrated that inductance can be exploited to improve some aspects of the performance of high speed integrated circuits. On the other hand, voltage overshoots due to inductance can increase the effective gate voltage stress so high that it may cause serious concern for gate oxide reliability in...
With aggressive scaling of CMOS technology, different performance parameters: latency, bandwidth, repeater power consumption and area, and delay variation of global interconnects are not scaling accordingly with those of devices and local interconnects. There have been various optimization schemes to minimize the discrepancy of performance between the devices and global interconnect lines. But these...
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