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In this paper, we aim to present a surface potential based model for GaN High Electron Mobility Transistors. The analytical model is computationally efficient and can be accurately used for DC and RF predictions. It includes various effects of velocity saturation, access region resistance, temperature, gate current and noise.
In this paper, quartz crystal resonators have been cut from a quartz crystal block usually used to grow new generations of quartz crystal blocks. The blank realization and the topology of the resonator prototype are exposed. The resulting resonators are SC-cut with a 5 MHz resonant frequency. Then, we report the first noise measurements made on these quartz crystal resonators. A comparison of these...
The expectation maximization algorithm is a popular approach to learning Gaussian mixture models from unlabeled data. In addition to the unlabeled data, in many applications, additional sources of information such as a-priori knowledge of mixing proportions are also available. We present a weakly supervised approach, in the form of a penalized expectation maximization algorithm that uses a-priori...
The paper presents an image authentication and secures message transmission technique by embedding message/image into color images. Authentication is done by embedding message/image by choosing image blocks of size 3 times 3 called mask from the source image in row major order. The position of insertion is chosen within the mask according to the formula k % s and (k + 1) % s + 1 where k and s are...
In this paper a masking based data hiding and image authentication technique (MDHIAT) has been proposed by embedding a message/image into a colour image. Bits from authenticating message/image are embedded in single bit position under each byte of the source image by choosing a standard 3 times 3 mask in row major order. Point of insertion of a bit is obtained by computing modulus operation of the...
This work focuses on the performance of a MWIR hole dominated APD. The superlattice (InAs/GaAs/GaInSb/AlSb/GaAs) was specifically designed to have hole dominated avalanching.
In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the...
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