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High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The tuning is fully automatic, and relies on a write-verify algorithm, with the optimal amplitude of each write pulse determined from runtime measurements, using a compact model of cell's dynamics, fitted to experimental results. The...
Potential advantages of specialized hardware for neuromorphic computing had been recognized several decades ago (see, e.g., Refs. [1, 2]), but the need for it became especially acute recently, due to significant advances of the computational neuroscience and machine learning. The most vivid example is given by the deep learning in convolution neuromorphic networks [3]: the recent dramatic progress...
This is a brief review of our recent work on memristor-based spiking neuromorphic networks. We first describe the recent experimental demonstration of several most biology-plausible spike-time-dependent plasticity (STDP) windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. We then discuss...
Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3∗3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training,...
We have investigated the area and latency tradeoffs with respect to error correcting capability of fast bit-parallel binary BCH ECC decoders. In particular, we show that for a primitive BCH code of length n over GF(2m) with a Hamming distance of at least 2t+1 the area and latency scale approximately as nm2t and mt, respectively. The results presented in this paper might be very useful, e.g., for assessing...
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