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This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical...
This paper analyses power-supply noise induced timing variations in NAND and NOR logical blocks. The focus of this work is on the NAND and NOR blocks used in nonover-lapping clock generation circuits used for switched capacitor sigma-delta analog-to-digital converters. Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using parameters from two manufacturing processes,...
This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for switched-capacitor (SC) sigma-delta (SigmaDelta) analog-to-digital converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo...
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