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This paper presents an extension of the BrainScaleS accelerated analog neuromorphic hardware model. The scalable neuromorphic architecture is extended by the support for multi-compartment models and non-linear dendrites. These features are part of a 65 nm prototype Application Specific Integrated Circuit (ASIC). It allows to emulate different spike types observed in cortical pyramidal neurons: NMDA...
We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in...
We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in...
This paper describes an operator for configuring scientific workflows that facilitates the process of assigning workflow activities to cloud resources. In general, modeling and configuring scientific workflows is complex and error-prone, because workflows are built of highly parallel patterns comprising huge numbers of tasks. Reusing tested patterns as building blocks avoids repeating errors. Workflow...
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