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This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of...
We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce a required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces a power to 56% in a 90-nm process technology, compared to the conventional...
We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that "1"s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either "0" or "1" with higher probability,...
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