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We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs, minimizes the power consumption and improves the functionality...
As the LHC luminosity is ramped up to 3×1034 cm-2 s-1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested...
Real time image analysis has undergone a rapid development in the last few years, due to the increasing availability of low cost computational power. However computing power is still a limit for some high quality applications. Highresolution medical image processing, for example, are strongly demanding for both memory (~250 MB) and computational capabilities allowing for 3D processing in affordable...
The silicon-vertex-trigger (SVT) at CDF is made of two pipelined processors: the associative-memory, AM, finding low precision tracks (roads) and the track-fitter, TF, refining the track quality with high-precision fits. We describe a next generation track fitter, the GigaFitter, that performs more than a fit per nanosecond. This device is based on modern FPGA technology, rich of powerful DSP arrays,...
The CDF associative-memory device, AM, proven technology developed for the Silicon-Vertex-Trigger at the CDF experiment, is one of the proposed solutions at CMS for track reconstruction at Level-1 in the Super-LHC very high-luminosity conditions (100 proton-proton collisions every 12.5 ns, at 1035 cm-2 sec-1). This luminosity requires a drastic revision of the existing trigger strategies. SVT is the...
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