The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A higher frequency, over 2 GHz, is suggested for current 4G or 5G wideband applications. By adopting a unique gain control method, an analog-controlled variable-gain amplifier (VGA) with an accurate dB-linear characteristic is presented. The designed VGA not only features large bandwidth, but also has accurate gain adjustment with a relatively wide control voltage range. The VGA has a measured gain...
A transformer-coupled frequency quadrupler with 50% bandwidth is designed in a 0.25μm SiGe process. The quadrupler covers an output frequency range from 36GHz to 60 GHz with a total power consumption of 38.5mW for a supply voltage of 2.5V. To fulfil the requirement of harmonic suppression, a novel on-chip asymmetrical Marchand balun structure is adopted to compensate the phase and amplitude errors...
This paper outlines the popular circuit tuning strategies reported for the implementation of reconfigurable low-noise amplifiers (LNAs). It presents a continuously-tuned LNA intended for multi-standard applications as well as enhancing the yield of conventional narrowband LNAs. The presented LNA is designed and implemented in a 0.25μm silicon-on-sapphire (SOS) CMOS process. It uses MOS-varactors at...
A low-voltage, low-power single-ended LNA is implemented in a 0.25µm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of −10 dBm and small-signal gain of 19.2 dB within the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.