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As one of the mostly used synchronization schemes in parallel programming on multi-core processors, barrier synchronization has been extensively studied in former research works. In conventional master-slave barrier or tree barrier, usually one centric core is selected to collect barrier arriving messages and to broadcast barrier releasing messages. Unfortunately the barrier core sometimes is deviated...
As one of the mostly used synchronization schemes in parallel programming, spin lock is supported in most off-the-shelf multi-/many-core processors. However the classical spin lock synchronization may lead to contention of acquiring the only lock and starvation of some threads busy waiting to be served. Thus queue-based spin lock has been put forwarded to eliminate both contention and unfairness issues...
Instruction fetching usually consumes more than 50% of total power in embedded processors. In DSP applications, instructions to be fetched may come from loops mostly. This paper proposes a loop unit of low-power microarchitecture for nested looping and it is fully compatible with RISC pipeline architecture. A loop instruction set is designed to finish different kinds of loops. Branching, jumping and...
Nowadays, the scratchpad memories (SPMs) are widely used as supplements or even alternatives for cache memories in audio applications on cost-effective SoCs. However, traditional SPM architectures encounter limitations of tight capacities and restricted data exchange methods with main memories. Such kinds of limitations significantly decrease the performance of the whole system, since most of the...
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