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Chip-to-wafer bonding is a promising technology for 3D integration due to high production yield using known good dies (KGDs). However, conventional chip-to-wafer 3D integration lowers production throughput because pick-and-place chip assembly is employed. To overcome the problem, we proposed a new chip-to-wafer 3D integration using self-assembly by which many KGDs can be simultaneously, rapidly, and...
We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously...
We developed a new self-assembled die bonder to produce three-dimensionally integrated circuit (3D IC) using a multichip-to-wafer bonding method in batch. In the self-assembled multichip bonder, large number of known good dies (KGDs) can be simultaneously transferred to an LSI wafer on which hydrophilic bonding areas with liquid droplets are prepared. The many KGD can be aligned to the bonding areas...
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