The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This failure analysis is based on a 28nm FPGA IDelay logic block which features an all programmable, 32-tap delay line. Each tap delay is carefully calibrated to provide an absolute delay value of 78ps independent of process voltage, and temperature variations. To locate the failing IDelay site, scan chain methodology was utilized. Combinations of delay tests were created to localize the defect within...
Global clocks are a dedicated network of interconnect specifically designed to reach all clock inputs to the various resources in an FPGA. These networks are designed to have low skew and low duty cycle distortion, low power, and improved jitter tolerance. They are also designed to support very high frequency signals. Faults in global clocks are very hard to isolate because it runs across the die...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.