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DAC architectures reported in the literature use segmentation schemes involving more thermometer and less binary bits, in order to guarantee a better dynamic and static performance. In this paper, a novel technique is proposed to minimize the glitch in the binary section of a segmented current steering DAC through the custom design of latches. This enables more bits in the binary section of the segmented...
In this paper, a tuning technique based on magnitude comparison is proposed for the first time for a composite source follower based second order low pass filter. This technique is targeted for continuous time Gm-C filters for low-frequency and low-power applications such as biomedical instruments. It uses direct tuning technique. The core tuning circuit consists of comparator, up-down counter, current...
The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch...
This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of Gm-C filters . The advantage of this scheme is that, instead of varying the power supply, the bias voltages at high impedance nodes are varied for frequency (F) tuning. A current steering DAC is proposed for controlling these bias voltages. Another major contribution of this paper is the use...
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