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In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4times4 multipliers which are designed both using LLA and GasP...
The quantum-dot cellular automata (QCA) implementation of digital logic circuits families has received popular attention. A QCA circuit because of its unique characteristics in terms of power consumption, speed and size of the circuit could be a great potential alternative for classical circuits. However, controls over the timing and fault-tolerance are significant issues in design and manufacturing...
In this paper, we investigate subthreshold pass-transistor logics for ultra-low-power applications. The performance characteristics of different pass-transistor XOR structures operating in the subthreshold region have been compared in 65nm and 90nm technologies. The results of the simulations show that the subthreshold logics have some advantages compared to their strong inversion counterparts. The...
In this paper, optical clocking systems are compared to electrical clocking systems. Three symmetrical optical clock distribution patterns, namely, H, X, and Y, are considered. The important factors for the optical distribution network are compared for different detector capacitances and clock tree shapes. The results show that the shape of clock distribution network does not have considerable impact...
In this paper, a static random access memory (SRAM) cell that reduces the gate leakage power with low access latency is proposed. The technique reduces the gate leakage current both in the zero and in the one states. The efficiency of the design is evaluated by simulating the circuit in a 45-nm CMOS technology. Compared to the conventional SRAM cell, the proposed design reduces the total gate leakage...
An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to get a proper transistor sizing. The simulation...
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