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Along with decrement in size of nanoelectronic devices, they are more prone to the effects of transient faults. Therefore, investigating the effects of such faults is of great importance. Due to high count of transistors in nanoelectronic devices, performing simulation by HSPICE is a time consuming process. Hence, several mathematical models have been proposed. However, our proposed model is simple...
In this paper, an analytical model for the HCI induced trap generation in the gate oxide and the degradation of a triple gate bulk FinFET is presented. The model which is obtained by solving the reaction-diffusion equations multi-dimensionally, includes the geometry dependence of the time-exponent of HCI degradation of the structure. In this framework, the electric field distribution and the maximum...
We report deriving a compact model for CNTFETs, using modified current- voltage relations, commonly used in modeling of CNTFETs. A carbon nanotube with 1.7 nm diameter and 5 nm length has been simulated with a layer of ZrO2 as oxide layer. The thickness of the oxide layer has been considered to be 2 nm. Density of states as a function of Fermi level is considered quadratic for both subthreshold and...
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