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In this paper, a new domino logic structure whose architecture is based on a leakage biased (LB) domino circuit is introduced. The proposed technique improves the performance and the dynamic power consumption of the circuits. In addition, the number of transistors is reduced leading to a lower silicon area. Simulations are done for various circuits. Compared to the LB method, in a full adder circuit,...
In this paper, we introduce a new topology for network on chips which is named multi-level mesh topology. The multi-level mesh topology is basically similar to the 2D-mesh with this difference that we have several meshes that have some common routers. This architecture reduces the latency and the dynamic power consumption in NoCs and can improve the communication throughput in high traffic applications...
In this paper, we introduce a topology for network on chips that is named cluster-mesh (CM) topology. This architecture reduces dynamic and static power consumption in NoCs and can reduce latency of communications in low traffic or local traffic applications. With cluster-mesh topology, area reduction in routers is about 44% and in links we can save more than 50% in area too. The dynamic power in...
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