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Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate leakage current. In this paper first it is shown that all of these challenges are functions of the MOS DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied...
On-chip MOS decoupling capacitors (DECAPs) are widely used to reduce power supply noise. Designing DECAP in nanotechnology designs provides many challenges. In this paper first it is shown that all of these challenges are functions of the DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied to 45 nm and 32 nm technology nodes and...
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