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In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32 nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall...
In this paper, we investigate the performance characteristic of CNFET inverter based on a new compact model. We consider temperature variation effects on the CNFET circuit performance implemented in a 32-nm technology. The results show in contrast to MOSFET sub-threshold current reduces in CNFET with temperature. So by using CNFET in high temperature applications we can obtain high speed and low leakage.
We report deriving a compact model for CNTFETs, using modified current- voltage relations, commonly used in modeling of CNTFETs. A carbon nanotube with 1.7 nm diameter and 5 nm length has been simulated with a layer of ZrO2 as oxide layer. The thickness of the oxide layer has been considered to be 2 nm. Density of states as a function of Fermi level is considered quadratic for both subthreshold and...
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