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It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been...
Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In [1, 2], authors proposed a comparison between LOC and LOS, showing that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. This shows the potential benefits of using LOS test scheme provided...
This study investigates the reasons why test power reduction through X-filling techniques works well for cycle-average power reduction but is not so efficient concerning instantaneous peak power reduction.
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this...
This paper presents design and implementation of a bi-directional inverter, including a high frequency transformer, a push-pull switch configuration at the dc side, a cycloconverter at the ac side, and a dsPIC controller. The dc/ac conversion is achieved with a phase-shifted control strategy. In addition, this topology also can achieve an ac/dc conversion with the PFC function. In this circuit, the...
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