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Our 3D stacked CMOS image sensor (CIS) has an ideal global shutter function with 16 million pixels and 4 million micro-bump interconnections placed at a 7.6-εm pitch between two silicon substrates, achieving interconnections with very low resistance. We confirmed the reliability of our 3D stacked interconnection technology by conducting reliability tests, which included heat cycle tests and high temperature...
We developed an efficient method for evaluating the 4 million micro-bump interconnection resistances of the 3D stacked 16-Mpixel CMOS image sensor by including vertical scanning and readout circuits and extra circuits in both of two substrates for a resistance testing mode, which enables us not only to find failed bumps but also to evaluate the resistances by scanning all micro bumps. We measured...
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