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For the disadvantage of high cost and poor practicability of traditional license plate recognition technology based on PC, apply this technology on the ZYNQ to implement the hardware acceleration of the license plate recognition algorithm. The platform consists of programmable logic (PL)and a processing system (PS). The hardware acceleration of the algorithm of license plate location is completed...
In this paper, we construct an analytical design framework for energy efficient scheduling for delay-constrained spectrum aggregation (ESSA), where the practical hardware limitations on SA capability bring various technical challenges. Specifically, the conventional water-filling power control cannot be adopted over all the channels, and the delay-aware scheduling solution should interact with the...
The recursive filter (IIR) parallel programming on SIMD is more difficult than that of nonrecursive algorithms due to data dependency. Several transformation methods for parallel coding of IIR filter on SIMD have already been proposed to deal with data dependency. However, the inherent prologue and epilogue in these methods obviously increase the complexity of control structures and induce extra hardware...
Motion trajectory tracing in indoor environment has become increasingly important, has the potential to support a broad array of applications including elder care, business analysis, pedestrian navigation. Traditional approaches involve wearable sensors, specialized hardware installations. This paper presents SmartMTra, an infrastructure-free, inertial sensor based motion trajectory tracing system...
A functional neural network for handwritten digits recognition using single binary RRAM as the synaptic weight element, was presented, with successful recognition rate is up to 81%. The results show that multilevel or continual resistances is not necessary for resistive device used as synaptic weight element in hardware neural network application. Variation of RRAM devices, sometimes, would not affect,...
Due to secondary code and AltBOC modulation,the primary code acquisition of the Galileo E5 signal can be complicated and requires additional hardware sources and algorithmic complexity in a receiver. In this paper, we propose a fast primary code acquisition technique for the Galileo E5 signal to reduce both hardware and algorithm complexities, while achieving a similar or better performance in receiver...
Performance tuning is an ongoing activity at most HPC sites. Small performance improvements can save thousands of dollars. Run-to-run performance variations significantly impact performance tuning. Not being able to tell which code version is faster (or more energy efficient) in a single run greatly increases the computational expense and uncertainty for theprogrammer. We will show examples where...
Based on the requirements of traditional video conference systems and the structure of MCU resource pool, a unified distributed resource pool system is proposed to achieve an integrated solution for conference resource deployment and management. The MCU resource pool architecture is designed by combining the cloud computing, virtualization, distributed resource management, and other core technologies...
In the scenarios of MICE (Meetings, Incentives, Conventions and Exhibitions) and other on-site face-to-face communications, one requirement is to conveniently discover surrounding PoI (People-of-Interest). In this paper, one relative localization method is proposed to accurately obtain the distances and azimuths from any person (one node) to his/her PoI (another node) in proximity. Specifically, the...
A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last, the results are XORed to obtain the CRC value...
Big data analytics is the process of examining large amounts of data of a variety of types (big data) to uncover hidden patterns, unknown correlations and other useful information. Its revolutionary potential is now universally recognized. Data complexity, heterogeneity, scale, and timeliness make data analysis a clear bottleneck in many biomedical applications, due to the complexity of the patterns...
This paper aims to detect human body based on Wireless Sensor Network (WSN). The experimental measurements are conducted in laboratory. A high quality network is obtained and then the Received Signal Strength Indicator (RSSI) can be calculated from the receive sensor module. The value of RSSI is used to do experiment and we get the conclusion that RSSI can be used for indoor person detection.
Modular multiplication is the most crucial component in RSA cryptosystem. In this paper, we present a new modular multiplication architecture using the Strassen multiplication algorithm and Montgomery reduction. The architecture is different from the interleaved version of Montgomery multiplication traditionally used in RSA design. By selecting different bases of 16 or 24 bits, it could perform 8,192-bit...
This paper presents an FPGA co-processor design for adaptive lane departure warning system, which requires intensive computation for real-time video image processing. The main functions of the co-processor include color scheme conversion, 2D filtering, transferring intensity into binary pattern using Otsu's threshold method, and detecting lanes using Hough transform. The system design is implemented...
ITRI container computer is a modular computer designed to be a building block for constructing cloud-scale data centers. Rather than using a traditional data center network architecture, which is typically based on a combination of Layer 2 switches and Layer 3 routers, ITRI containercomputer's internal interconnection fabric, called Peregrine, is specially architected to meet the scalability, fast...
With the shift to chip multiprocessors, managing shared resources has become a critical issue in realizing their full potential. Previous research has shown that thread mapping is a powerful tool for resource management. However, the difficulty of simultaneously managing multiple hardware resources and the varying nature of the workloads have impeded the efficiency of thread mapping algorithms. To...
To date, most research on software code cloning has concentrated on detection and analysis techniques and their evaluation, and most empirical studies of cloning have investigated cloning within single system versions. In this paper, we present the results of a longitudinal study of cloning among the SCSI drivers for the Linux operating system that spans 16 years of evolution. We have chosen the SCSI...
Virtualization is a common technology for improving the utilization of existing physical computing resources, which provides great opportunity for industry growth and research due to its high flexibility and simplification. While various software products are available for providing the infrastructure of virtualization, the deploy for a specific industry area is still challenging. We attempt to apply...
This paper presents a practical and general coder and decoder of network coding (NC) with HDL (Hardware Description Language) logic for wire-speed nodes in multisource multicast networks. The NC coders apply random linear network coding (RLNC) and the decoders recover the original packets by Cramer's rule. All these mathematical operations are carried out in the Galois Field (256). The structures...
For higher processing and computing power, chip multiprocessors (CMPs) have become the new mainstream architecture. This shift to CMPs has created many challenges for fully utilizing the power of multiple execution cores. One of these challenges is managing contention for shared resources. Most of the recent research address contention for shared resources by single-threaded applications. However,...
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